Higher integration of semiconductor devices is required to satisfy consumer demands for superior performance and inexpensive prices. With semiconductor memory devices, integration is an important factor in determining product price, and hence increased integration may be especially important. The integration level of typical two-dimensional or planar semiconductor memory devices is often primarily determined by the area occupied by a unit memory cell, and hence integration is greatly influenced by the level of fine pattern forming technology. However, since extremely expensive semiconductor equipment is needed for increasing pattern fineness, integration of two-dimensional memory devices is increasing but is still limited.
To overcome this limitation, there has been proposed a technology of forming memory cells in three-dimensions, for example, US Patent Publication No. 2007/0252201 (Kito et al.) entitled “Nonvolatile semiconductor memory device and manufacturing thereof”. In this cited reference, vertical semiconductor pillars are used as active regions, and memory cells are formed in three-dimensions. By doing so, the area of a semiconductor substrate can be used more effectively and thus integration can be greatly increased as compared to typical two-dimensional semiconductor memory devices. Also, since the technology disclosed in the cited reference is not based on a method of repeated forming of memory cells in two-dimensions, but on a method of forming word lines by using a patterning process for defining an active region, manufacturing cost per bit can be greatly reduced.